The Strategy Pattern in SystemVerilog

I had watched a wonderful video series of Object Oriented Design Patterns on called "Foundations of Programming: Design Patterns" by Elisabeth Robinson and Eric Freeman.  In their series, they go through some of the ideas in "Design Patterns" and have very concise code examples that illustrate specific Design Patterns.

I highly recommend checking out "Foundations of Programming: Design Patterns" and checking out - if you haven't heard of them before.

The example code from the video series is, of course, not written in SystemVerilog.  It is written in Java.  From the site you can download for free the Java example code.  As an interested student, I took their example code and rewrote it in SystemVerilog, staying as close as possible to the original and published the result on GitHub below.

Strategy Pattern in SystemVerilog on GitHub

The example to illustrate the Strategy Pattern was the MiniDuckSimulator.  It uses four concrete implementations of a Duck: MallardDuck, RubberDuck, DecoyDuck, ModelDuck.  And uses two abstract behaviors: QuackBehavior and FlyBehavior, which have various concrete implementations that are implemented via the Strategy Pattern.  For a better description, see the video series above.

Some interesting things to note: some of the language constructs to do this implementation are only available in the IEEE SystemVerilog1800-2012 specification.  For example "interface class" is a new construct only described in the 2012 specification.  The "implements" construct is also new to the 2012 specification.  The implementation of the Strategy Pattern in SystemVerilog was able to be very cleanly realized with the 2012 SystemVerilog specification and Mentor Questa.

I am curious if the rest of the Design Patterns are able to be done cleanly in SystemVerilog.