If you are using a graphical version of Emacs, you sometimes need to make things bigger or smaller depending on what you want to see or show to someone at your desk.
There are two ways to to this.
I am excited to share my latest paper which was recently published at DVCon 2017 in San Jose, California. The full title is:
"Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation"
Constrained Random simulation is so critical to modern verification environments that it is a major component of the SystemVerilog language itself. This paper proposes a method that improves how UVM Constrained Random simulations are run. By abstracting the purpose of a simulation to be achieving “Objective Functions” (nominally coverage goals), it is possible to have the simulation autonomously explore deep possibilities from multiple points in time of a standard UVM testbench governed by feedback. This method has a number of benefits including: faster automated coverage closure, an efficient final stimulus solution and proposed higher quality of coverage.
I'm honored to share that my paper:
"Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012"
was awarded Best Paper at the Design and Verification Conference (DVCon) 2016. The link to the final paper is now available.
The SystemVerilog bind command allows for adding new functionality to a module. Typically, it is used to add new checking to a RTL block.
I wrote the example code (available on GitHub here) below to demonstrate a feature of bind that allows the binded module to parameterize itself based on where it is being used. When you think about what bind is actually doing it starts to make sense.
Squarespace has the ability to syntax highlight the following three source types:
in a very workable built in code block in their blogging system. But, if you use another source type like SystemVerilog or Python you will have to figure out something else to get your source code syntax highlighted on Squarespace.
To handle something like SystemVerilog, or nearly every language, the solution I ended up with was using Emacs with the plugin htmlize. The idea is that since Emacs already has great syntax highlighting for everything, you can export regions or whole files to raw HTML with that syntax highlighting intact.
I hadn't used Emacs to compile and parse errors for Mentor Questa before and decided to see what that would be like. Making Emacs understand how the simulator works and spits out errors involves extending Emacs to know how to launch your Verilog simulator and how to interpret the console messages. The built in Emacs compilation mode is not terrible and at least gives a starting point for compiling and debugging standard languages and custom ones. This is how to do it with Mentor Questa.