Design Patterns

Humble Book Bundle of O'Reilly Books - Head First Design Patterns

A few years ago I wrote a paper for the Design and Verification Conference inspired by the book “Head First Design Patterns” by Robson and Freeman. “Head First Design Patterns” is an excellent way to learn about Design Patterns. I liked the style of the book, which was lighthearted and written in a conversational tone. It made learning about Design Patterns actually fun!

I have a paper copy, of course, of the book. But, I saw that Humble Bundle had a “Head First Series by O’Reilly” bundle sale for the next week which includes “Head First Design Patterns” in ebook and PDF formats.

If you are looking for a cost effective way of getting “Head First Design Patterns” and other O’Reilly Head First Books this is a great way to get them. This is not an affiliate link and I get no kick back, but I wanted to share it with you since I loved the book. A large and configurable portion of the proceeds go to charity when using this Humble Bundle. The charity in this case is Code for America, a non-profit.

In order to get “Head First Design Patterns” you would need to buy it at the $15 or above level. I just bought it myself and am happy to now have an electronic copy of this book! The bundle ends on Oct 14, 2018.

Humble Book Bundle: Head First Series by O’Reilly

The Strategy Pattern in SystemVerilog

The Strategy Pattern in SystemVerilog

I had watched a wonderful video series of Object Oriented Design Patterns on called "Foundations of Programming: Design Patterns" by Elisabeth Robinson and Eric Freeman.  In their series, they go through some of the ideas in "Design Patterns" and have very concise code examples that illustrate specific Design Patterns.

I highly recommend checking out "Foundations of Programming: Design Patterns" and checking out - if you haven't heard of them before.

The example code from the video series is, of course, not written in SystemVerilog.  It is written in Java.  From the site you can download for free the Java example code.  As an interested student, I took their example code and rewrote it in SystemVerilog, staying as close as possible to the original and published the result on GitHub below.