I'm honored to share that my paper:
"Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012"
was awarded Best Paper at the Design and Verification Conference (DVCon) 2016.
My paper is now available from the DVCon Website under the DVCon 2016 Proceedings and as a PDF file here.
DVCon is an annual electronic industry conference held in San Jose, California and was attended by 1177 people this year. From the description from their webpage "DVCon is the premier conference for discussion of functional design and verification of electronic systems". I found it energizing to be surrounded by people who are performing the same role that I do, but at different companies, and learning how they do their job. Everyone approaches the problem of electronic design and verification differently which is absolutely fascinating.
Eldon Nelson (left) and Ambar Sarkar, DVCon Program Chair (right) at Awards Presentation
All of the speakers at DVCon were wonderful, taking time to share how they do something or their proposal to improve a process. I was fortunate to have speakers during my presentation session whom I really admire. The charismatic John Aynsley of Doulos spoke just before me with a great speech and I was thrilled to have Clifford Cummings of Sunburst follow me. Cummings has an enormous number of papers in the field published. Aynsley has a Youtube channel focused on verification, and I witnessed one of his many Youtube fans, perhaps awkwardly, approach him the night before the conference. And not to leave out Mike Horn of Mentor, whom I've run into many times when working through some great engineering problems when I worked at Micron Technology, was the last speaker.
I'd like to thank Intel, my employer, for sponsoring me to attend the conference. And I'd like to thank the attendees who actually had to actively vote at the conference - thank you! I hope to be back in years to come with more things I just can't wait to share.