I had used other programming languages before working with System Verilog. So when I started looking at System Verilog code for the first time, I was perplexed why there were all of these `includes all over - even in purely object oriented verification logic.
There is a problem and proposed solution I would like to share. Using packages instead of `include to store constants. I wrote the example both ways: package and `include; so you can see something that I see typically done with `include done with packages.